MC9S08xxx Series Features

8-Bit HCS08 Central Processor Unit (CPU)

•48-MHz HCS08 CPU (central processor unit)

•24-MHz internal bus frequency

•HC08 instruction set with added BGND instruction

•Background debugging system

•Breakpoint capability to allow single breakpoint

setting during in-circuit debugging (plus two more

breakpoints in on-chip debug module)

• In-circuit emulator (ICE) debug module containing

two comparators and nine trigger modes. Eight

deep FIFO for storing change-of-flow addresses

and event-only data. Debug module supports both

tag and force breakpoints.

• Support for up to 32 interrupt/reset sources

•ADC

— 12-channel, 12-bit analog-to-digital

converter with automatic compare function;

internal temperature sensor

•ACMP

— Analog comparator with option to

compare to internal reference; operation in stop3

mode

•SCI

— Two serial communications interface

modules with optional 13-bit break LIN extensions

•SPI

— Two 8- or 16-bit selectable serial peripheral

interface modules with a receive data buffer

hardware match function

•IIC

— Inter-integrated circuit bus module to

operate at up to 100 kbps with maximum bus

loading; multi-master operation; programmable

slave address; interrupt-driven byte-by-byte data

transfer; 10-bit addressing and broadcast modes

support

•Timers

— One 2-channel and one 6-channel

16-bit timer/pulse-width modulator (TPM)

modules: Selectable input capture, output

compare, and edge-aligned PWM capability on

each channel. Each timer module may be

configured for buffered, centered PWM (CPWM)

on all channels

•KBI

— 8-pin keyboard interrupt module

•RTC

— Real-time counter with binary- or

decimal-based prescaler

Memory Options

• Up to 60 KB of on-chip in-circuit programmable

flash memory with block protection and security

options

• Up to 4 KB of on-chip RAM

• 256 bytes of USB RAM

Clock Source Options

• Clock source options include crystal, resonator,

external clock

• MCG (multi-purpose clock generator) — PLL and

FLL; internal reference clock with trim adjustment

System Protection

• Optional computer operating properly (COP) reset

with option to run from independent 1-kHz internal

clock source or the bus clock

• Low-voltage detection with reset or interrupt

• Illegal opcode detection with reset

• Illegal address detection with reset

Input/Output

• Up to 51 general-purpose input/output pins

• Software selectable pullups on ports when used

as inputs

• Software selectable slew rate control on ports

when used as outputs

• Software selectable drive strength on ports when

used as outputs

• Master reset pin and power-on reset (POR)

• Internal pullup on RESET, IRQ, and BKGD/MS

pins to reduce customer system cost

Power-Saving Modes

• Wait plus two stops

Package Options

•64-pin quad flat package (QFP)

•64-pin low-profile quad flat package (LQFP)

•48-pin quad flat no-lead (QFN)

•44-pin low-profile quad flat package (LQFP)

Peripherals

•USB —

USB 2.0 full-speed (12 Mbps) device

controller with dedicated on-chip USB transceiver,

3.3-V regulator and USBDP pull-up resister;

supports control, interrupt, isochronous, and bulk

transfers; supports endpoint 0 and up to 6

additional endpoints; endpoints 5 and 6 can be

combined to provide double buffering capability

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